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E2E1032-27-Y4
Semiconductor MSM66562/66P563
Semiconductor
el im This MSM66562/66P563 ina version: Jan. 1998 ry Previous version: Nov. 1996
Pr
High-speed High-performance 16-Bit Microcontroller for Compact System
GENERAL DESCRIPTION
The MSM66562/66P563 is a high-speed, high-performance 16-bit microcontroller that employs OKI original nX-8/500S CPU core. The MSM66562/66P563 includes a 16-bit CPU, ROM, RAM, a 8-bit A/D converter, serial ports, capture/compare timers, and I/O ports.
FEATURES
* Program memory space Internal ROM * Data memory space Internal RAM * High-speed execution Minimum instruction execution time * Rich instruction set : : : : 32K bytes 16K bytes (MSM66562), 32K bytes (66P563) Internal RAM only 0.5K bytes (MSM66562), 1K bytes (MSM66P563)
* Abundant addressing modes
: 100 nsec (@ 20 MHz) : Instruction set superior in orthogonal matrix 8/16-bit data transfer instructions 8/16-bit arithmetic instructions Multiplication and division operation instructions Bit manipulation instructions Bit logic instructions ROM table reference instructions : Register addressing Page addressing Pointing register indirect addressing Stack addressing Immediate addressing
* I/O port Input ports (or analog input ports) : 6 channels Input-output ports : 27 bits (Each bit can be configured to be an input or output) * Capture (CAP)/Compare (CMP) timers Free run counters : 16 bits 1 16-bit CAP :1 16-bit CMP :3 16-bit CAP/CMP :2 * 16-bit general timer (also usable for 2ch 8 bits) : 1 8-bit geneal counter (or baud rate generator) : 1 * 8-bit serial ports UART mode :1 * 8-bit A/D converter : 6 channels * Interrupts Maskable : Internal 12/external 2 (2-level priority can be set) * ROM window function
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Semiconductor * Standby modes HALT mode STOP mode * Package: 42-pin plastic Shrink DIP (SDIP42-P-600-1.78) 64-pin plastic QFP (QFP64-P-1414-0.80-BK)
MSM66562/66P563
(Product name: MSM66562-RS) (Product name: MSM66P563-RS) (Product name: MSM66562-GS-BK) (Product name: MSM66P563-GS-BK indicates a code number.
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P5_0/CAP0 CPU Core Control Registers * RAM 512 Bytes PSW PC * ROM 16K Bytes ALU Instruction Decoder ALU Control ACC Memory Control Pointing R Local R.
Bus Port Control
EA ALE/P3_0 PSEN/P3_1
BLOCK DIAGRAM
Semiconductor
P5_1/CMP0 P5_2/CMP1 P5_3/CMP2 SSP LRB
CAP/CMP Timer
AD0/P0_0 AD7/P0_7 A8/P1_0 A14/P1_6
P5_4/CPCM0 P5_5/CPCM1
General Timer
P7_0/RXD0
Serial Port
P7_1/TXD0
P12_0/AI0
A/D Converter System Control Port Control
P12_5/AI5
P0
P1
P3
P5
P6
P7
RES
P12
OSC0
OSC1
P6_0/INT0 P6_1/INT1
Interrupt
MSM66562/66P563
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*
MSM66P563 (OTP version) contains 32K bytes ROM and 1K bytes RAM.
Semiconductor
MSM66562/66P563
PIN CONFIGURATION (TOP VIEW)
TEST CAP0/P5_0 CMP0/P5_1 CMP1/P5_2 CMP2/P5_3 CPCM0/P5_4 CPCM1/P5_5 GND OSC0
1 2 3 4 5 6 7 8 9
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
AD0/P0_0 AD1/P0_1 AD2/P0_2 AD3/P0_3 AD4/P0_4 AD5/P0_5 AD6/P0_6 AD7/P0_7 ALE/P3_0 PSEN/P3_1 VDD GND A8/P1_0 A9/P1_1 A10/P1_2 A11/P1_3 A12/P1_4 A13/P1_5 A14/P1_6 TXD0/P7_1 RXD0/P7_0
OSC1 10 VDD 11 INT0/P6_0 12 INT1/P6_1 13 RES 14 EA 15 AI0/P12_0 16 AI1/P12_1 17 AI2/P12_2 18 AI3/P12_3 19 AI4/P12_4 20 AI5/P12_5 21
42-Pin Plastic Shrink DIP
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PIN CONFIGURATION (TOP VIEW) (Continued)
Semiconductor
P3_1/PSEN 13 P3_0/ALE 14 P0_7/AD7 15 NC 16 P1_0/A8 P1_1/A9 GND VDD NC NC NC NC NC 11 NC 12 NC 9 NC 10 8 7 6 5 4 3 2 1 NC 17 P0_6/AD6 18 P0_5/AD5 19 P0_4/AD4 20 P0_3/AD3 21 P0_2/AD2 22 P0_1/AD1 23 P0_0/AD0 24 TEST 25 P5_0/CAP0 26 P5_1/CMP0 27 P5_2/CMP1 28 P5_3/CMP2 29 P5_4/CPCM0 30 P5_5/CPCM1 31 NC 32 34 GND 33 NC 36 OSC1 35 OSC0 38 NC 37 NC 40 NC 39 NC 42 NC 41 VDD 44 NC 43 NC 46 P6_1/INT1 45 P6_0/INT0 48 NC 47 RES 64 NC 63 P1_2/A10 62 P1_3/A11 61 P1_4/A12 60 P1_5/A13 59 P1_6/A14
NC : No connection pin
64-Pin Plastic QFP
58 P7_1/TXD0 57 P7_0/RXD0 56 P12_5/AI5 55 P12_4/AI4 54 P12_3/AI3 53 P12_2/AI2 52 P12_1/AI1 54 P12_0/AI0 50 EA 49 NC
MSM66562/66P563
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Semiconductor
MSM66562/66P563
PIN DESCRIPTION
Symbol P0_0-P0_7/ AD0-AD7 P1_0-P1_6/ A8-A14 P5_0/CAP0 P5_1-P5_3/ CMP0-CMP2 P5_4-P5_5/ CPCM0-CPCM1 P6_0/INT0 P6_1/INT1 Type I/O Description P0: 8-bit input-output port. Each bit can be assigned to be an input or an output. AD: When an external memory is used, these pins output the lower 8 bits of the address. These pins also input or output the data. P1: 7-bit input-output port. Each bit can be assigned to input or output. A: When an external memory is used, these pins output the upper 8 bits of the address. P5: 6-bit input-output port. Each bit can be assigned to input or output. CAP : Capture input pin CMP: Compare output pin CPCM: Capture input pin or compare output pin P6: 2-bit input-output port. Each bit can be assigned to input or output. INT0/1: External interrupt request input pin P3: 2-bit input-output port. Each bit can be assigned to input or output. PSEN: Strobe pulse output pin to fetch to external program memory ALE: Timing pulse output pin to latch the lower 8 bits of the address output from port 0 when the CPU accesses the external memory P7: 2-bit input-output port. Each bit can be assigned to input or output. RXD0 : SCI0 Receiver data input pin TXD0 : SCI0 Transmitter data output pin P12: 6-bit input port Analog signal input pin for A/D converter Basic clock oscillation pin Low-active RESET input pin Normally set to "H" level. If set to "L" level, the program memory goes into external access mode and accesses external program memory Power supply pin Ground pin Be sure to connect this pin to VDD. Test pin for outgoing inspection.
I/O
I/O
I/O
P3_0/PSEN P3_1/ALE
I/O
P7_0/RXD0 P7_1/TXD0 P12_0-P12_5 AI0-AI15 OSC0 OSC1 RES EA VDD GND TEST
I/O I I I O I I I I I
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Semiconductor
MSM66562/66P563
REGISTERS
Accumulator Control Register (CR) Program Status Word
15 ACC 0
15 PSW
0
Bit 15 : Carry flag (CY) Bit 14 : Zero flag (ZF) Bit 13 : Half carry flag (HC) Bit 12 : Data descriptor (DD) Bit 11 : Sign flag (S) Bit 10 : User flag (F2) Bit 9 : Overflow flag (OV) Bit 8 : Master interrupt enable flag (MIE) Bit 7 : Multiply and accumulate operation bank flag (MAB)* Bit 6 : User flag (F1) Bit 5 : Bank common base (BCB1)* Bit 4 : Bank common base (BCB0)* Bit 3 : User flag (F0) Bit 2-0 : System control base 2-0 (SCB2-0) * Bit 7 (MAB), Bit 5 (BCB1), and Bit 4 (BCB0) can be used as the User flag. 15 0 PC LRB SSP
Program Counter Local Register Base System Stack Pointer Pointing Register (PR)
15
0
Index Register 1 Index Register 2 Data pointer User Stack Pointer
X1 X2 DP USP
Local Register
7 ER0 ER1 ER2 ER3 R1 R3 R5 R7 07 R0 R2 R4 R6 0
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Semiconductor
MSM66562/66P563
SFR
Address [H] 0000 0001 0002 0003 0004 0005 0006 0007 0008I 0009 000A 000B 000CI 000D 000E 000FI 0010 0011 0012 0013 0014 0015 0016 0017 0018 0019I 001A 001B 001C 001DI 001EI 001FI 0020 0021I 0022 0023I 0024 0025I 0026I 0027I Port 5 Mode Register Port 6 Mode Register Port 7 Mode Register P5IO P6IO P7IO -- -- -- R/W 8 00 00 00 Port 3 Mode Register P3IO -- R/W 8 00 Port 5 Data Register Port 6 Data Register Port 7 Data Register Port 0 Mode Register Port 1 Mode Register P5 P6 P7 P0IO P1IO -- R/W 8 -- R/W 8 C0 00 00 00 00 Port 3 Data Register P3 -- R/W 8 00 Port 0 Data Register Port 1 Data Register P0 P1 -- R/W 8 00 00 Stop Code Acceptor Standby Control Register STPACP SBYCON -- -- W R/W "0" C8 ROM Window Register ROM Ready Control Register ROMWIN ROMRDY -- -- R/W 8 00 8B Name System Stack Pointer Local Register Base Program Status Word Accumulator Abbreviated Abbreviated 8/16 R/W Name (BYTE) Name (WORD) Operation -- LRBL LRBH PSWL PSWH ACCL ACCH SSP LRB PSW ACC R/W 8/16 16 Reset Status FFFF Undefined 0000 0000 0000 0000
I mark in the address column indicates that there is a nonexistent bit in its register.
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Semiconductor
MSM66562/66P563
SFR (Continued)
Address [H] 0028 0029I 002A 002BI 002C 002DI 002EI 002FI 0030 0031I 0032 0033I 0034 0035I 0036 0037 0038I 0039I 003AI 003BI 003C 003D 003E 003FI 0040 0041 0042 0043 0044 0045 0046 0047 0048 0049 004A 004B 004C 004D 004E 004F I mark in the address column indicates that there is a nonexistent bit in its register. Interrupt Priority Control Register 7 Free Run Counter Capture Register 0 Compare Out Register 0 Compare Out Register 1 Compare Out Register 2 Capture Compare Register 0 Capture Compare Register 1 IP7 -- -- -- -- -- -- -- -- FRC CAPR0 CMPR0 CMPR1 CMPR2 CPCMR0 CPCMR1 R/W 16 R/W R/W R 8 00 0000 Undifined 0000 0000 0000 0000 0000 Interrupt Enable Register 3 Interrupt Priority Control Register 0 Interrupt Priority Control Register 1 Interrupt Priority Control Register 2 Interrupt Priority Control Register 3 IE3 IP0 IP1 IP2 IP3 -- -- -- --- --- R/W 8 R/W 8 00 F0 00 00 00 Interrupt Request Register 3 Interrupt Enable Register 0 Interrupt Enable Register 1 IRQ3 IE0 IE1 -- -- -- R/W R/W 8 8 00 00 00 Port 5 Secondary Function Control Register Port 6 Secondary Function Control Register Port 7 Secondary Function Control Register Interrupt Request Register 0 Interrupt Request Register 1 P5SF P6SF P7SF IRQ0 IRQ2 -- -- R/W 8 -- R/W 8 00 00 00 00 00 Port 3 Secondary Function Control Register P3SF -- R/W 8 00 Name Port 1 Secondary Function Control Register Port 2 Secondary Function Control Register Abbreviated Abbreviated R/W 8/16 Name (BYTE) Name (WORD) Operation P0SF P1SF -- R/W 8 Reset Status 00 00
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Semiconductor
MSM66562/66P563
SFR (Continued)
Address [H] 0050P 0051P 0052P 0053P 0054P 0055P 0056P 0057 0058P 0059 005AP 005B 005C 005D 005E 005F 0060P 0061P 0062 0063 0064 0065 0066 0067 0068 0069 006A 006B 006CP 006DP 006E 006F 0070 0071 0072P 0073 0074 0075 0076 0077 I mark in the address column indicates that there is a nonexistent bit in its register. 8-bit General Timer 3 Counter 8-bit General Timer 3 Register 8-bit General Timer 3 Control TM3C TM3R TM3CON -- -- -- R/W 8 Undifined Undifined 70 8-bit General Timer 1 Counter 8-bit General Timer 2 Counter 8-bit General Timer 1 Register 8-bit General Timer 2 Register 8-bit General Timer 1 Control 8-bit General Timer 2 Control TM1C TM2C TM1R TM2R TM1CON TM2CON TBCKDV R/W TBCKDV -- -- R/W 8 8/16 Undifined 70 40 Undifined TBC Clock Dividing Counter TBC Clock Dividing Register TBCKDVR -- TBCKDV R/W R 8/16 16 F0 F0 External Interrupt Control Register 1 EXI2CON -- R/W 8 4C External Interrupt Control Register 0 EXI0CON -- R/W 8 00 Name Free Run Counter Control Register Capture Control Register Compare Out Control Register 0 Compare Out Control Register 1 Compare Out Control Register 2 Abbreviated Abbreviated 8/16 R/W Name (BYTE) Name (WORD) Operation FRCON CAPCON CMPCON0 CMPCON1 CMPCON2 -- -- -- -- -- -- -- R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8 Reset Status C0 C0 FC FC FC FC FC
Capture Compare Control Register 0 CPCMCON0 Capture Compare Control Register 1 CPCMCON1
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Semiconductor
MSM66562/66P563
SFR (Continued)
Address [H] 0078 0079 007A 007B 007C 007D 007E 007F 0080P 0081P 0082 0083P 0084 0085 0086 0087 0088 0089 008A 008B 008C 008D 008E 008F 0090 0091 0092 0093 0094 0095 0096 0097 0098 0099 009A 009B 009C 009D 009E 009F I mark in the address column indicates that there is a nonexistent bit in its register. SIO0 Transmit Control Register SIO0 Receive Control Register SIO0 Transmit/Receive Buffer Register SIO0 Status Register ST0CON SR0CON SI0BUF S0STAT -- -- -- -- R/W 8 05 09 Undifined C0 Name Abbreviated Abbreviated 8/16 R/W Name (BYTE) Name (WORD) Operation Reset Status
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Semiconductor
MSM66562/66P563
SFR (Continued)
Address [H] 00C8 00C9 00CA 00CB 00CC 00CD 00CE 00CF 00D0 00D1 00D2 00D3 00D4 00D5 00D6 00D7 00D8 00D9 00DA 00DB 00DC 00DD 00DE 00DF 00E0 00E1 00E2 00E3 00E4 00E5 00E6 00E7 00E8 00E9 00EA 00EB 00EC 00ED 00EE 00EF I mark in the address column indicates that there is a nonexistent bit in its register. Name Abbreviated Abbreviated R/W 8/16 Name (BYTE) Name (WORD) Operation Reset Status
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Semiconductor
MSM66562/66P563
SFR (Continued)
Address [H] 00F0 00F1 00F2 00F3 00F4 00F5 00F6 00F7 00F8 00F9 00FA 00FB 00FC 00FD 00FE 00FF I mark in the address column indicates that there is a nonexistent bit in its register. Emulator Use Area (Do not access this area.) Name Abbreviated Abbreviated R/W 8/16 Name (BYTE) Name (WORD) Operation Reset Status
Notes: 1. 2. 3. 4. 5. 6.
Do not write a read-only SFR. Do not read a write-only SFR. Do not provide 16-bit manipulation to 8-bit manipulation only SFR. Do not provide 8-bit/1-bit manipulation of to 16-bit manipulation only SFR. Do not access the addresses which are not allocated with a register. Do not access the emulator application area.
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Semiconductor
MSM66562/66P563
ADDRESSING MODES
The MSM66562/66P563 provides independent 0.5K-byte data (1K bytes for MSM65P63) and 32K-byte program spaces with various types of addressing modes. These modes are shown below for both RAM (for data space) and ROM (for program space). RAM Addressing Mode (for data space) * Register addressing
Example INC USP USP
* Page addressing a) sfr page
Example L A, sfr IRQ0 SFR 0000H 0040H
b) Fixed page
Example ST A, fix 0C0H RAM 0200H 02C0H
c) Current page
Example ROR off 078H RAM xx00H xx78H
* Direct data addressing
Example CLR dir 380H RAM 0300H 0380H
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Semiconductor * Pointing register indirect addressing a) DP/X1 indirect
Example
XCHG A, [DP]
DP
b) Post increment DP indirect
Example
ADD A, [DP+]
DP After access, DP is incremented by 2.
c) Post decrement DP indirect
Example
SUB A, [DP-]
DP After access, DP is decremented by 2.
d) DP/USP indirect with 7-bit displacement
Example
AND A, 12[DP]
DP
e) X1/X2 indirect with 16-bit base
Example
XOR A, 1234H[X1] X1
f) X1 indirect with 8-bit register (A, R0) displacement
Example
OR A, [X1+A]
X1

RAM RAM RAM -64 to +63 RAM
MSM66562/66P563
0-65535
RAM
AL
RAM
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Semiconductor
* Special bit area addressing a) Fixed page SBA area (02C0H to 02FFH)
Example
SB sbafix 2D1H.3
b) Current page SBA area (C0H to FFH)
Example
RB sbaoff 2E9H.7
ROM Addressing Mode (for program space) * Immediate addressing
Example
MOV SSP, #3FFH
* Table data addressing TSR specifies the address segment. a) Direct
Example LC A, 5678H
b) RAM addressing indirect
Example
CMPC A, [USP]
USP
c) RAM addressing indirect with 16-bit base
Example LC A, 1234H[ER0] RAM ER0

RAM 02C0H 02D1H RAM C0H E9H
ROM
Address
MSM66562/66P563
xxxxH
ROM
5678H
ROM
0-65535
ROM
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Semiconductor
MSM66562/66P563
MEMORY MAP
Program Memory Space
0000H Vector table area (74 bytes) 0049H 004AH 0069H 006AH VCAL table area (32 bytes)
Internal ROM area
0FFFH 1000H ACAL area (2K bytes) 17FFH 1800H
3FFFH 4000H External ROM area* 7FFFH
*
For MSM66P563 (OTP version), 4000H to 7FFFFH are in the internal ROM area.
Data Memory Space *2
00FFH 0100H 01FFH 0200H 02FFH 0300H 03FFH SFR Area Expanded SFR Area FIX Area *1 Internal RAM Area Area where local register can be set 01FFH 0200H Expanded SFR Area
X1 X2 DP USP X1 X2 DP USP X1 USP X1 X2 DP USP
SCB=0 SCB=1
0208H 0210H 0238H 0240H
Pointing Register Set
SCB=7
02C0H SBA Area (64 bytes) 0300H
Area where SB, RB, JBS, and JBR instructions can be performed in shorter byte count.
*1 For MSM66P563 (OTP version), 200H to 5FFH are in the internal RAM area. *2 1000H to 7FFFH inthe data space (also can be used as a ROM window area. 17/24
Semiconductor
MSM66562/66P563
ABSOLUTE MAXIMUM RATINGS
(Ta=25C) Parameter Power Supply Voltage Input Voltage Output Voltage Analog Input Voltage Power Dissipation Storage Temperature Symbol VDD VI VO VAI PD TSTG Ta=85C GND=0 V Ta = 25C Per package Per output -- Condition Rating -0.3 to 7.0 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to VDD -- 50 -50 to +150 V Unit
mW C
RECOMMENDED OPERATING CONDITIONS
Parameter Digital Power Supply Voltage Analog Input Voltage Memory Hold Voltage Operating Frequency Ambient Temperature Fan Out Symbol VDD VAI VDDH fOSC Ta N Condition fOSC20 MHz -- fOSC=0 Hz VDD=5 V10% -- MOS load TTL load P0, P3_0, P3_1 P1, P5, P6, P7 Range 4.5 to 5.5 GND to VDD 2.0 to 5.5 0 to 20 -40 to +85 20 2 1 Unit V MHz C --
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Semiconductor
MSM66562/66P563
ELECTRICAL CHARACTERISTICS
DC Characteristics (Preliminary)
(VDD=5 V10%, Ta=-40 to +85C) Parameter H Level Input Voltage L Level Input Voltage H Level Output Voltage H Level Output Voltage L Level Output Voltage L Level Output Voltage Input Leakage Current Input Current Input Current H Level Output Current H Level Output Current L Level Output Current L Level Output Current Input Capacitance Output Capacitance Current Consumption (in STOP mode) Current Consumption *2 (in HALT mode) Current Consumption *2 1 1 1, 4 2 1, 4 2 3, 6 5 7 1, 4 2 1, 4 2 IOH VO=2.4 V IOL ILO CI CO IDDS IDDH IDD VO=VDD/0 V f=1 MHz, Ta=25C VDD=2 V, Ta=25C* *1 fOSC=20 MHz No load IIH/IIL VI=VDD/0 V
H Level Input Voltage 2, 4, 5, 6, 7
Symbol VIH VIL VOH VOL
Condition -- -- IOH=-400 mA IOH=-200 mA IOL=3.2 mA IOL=1.6 mA
Min. 2.2 0.80VDD -0.3 -0.3 VDD-0.4 VDD-0.4 -- -- -- -- -- -2 -1 10 5 -- -- -- -- -- -- --
Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 5 7 0.2 1
Max. VDD+0.3 VDD+0.3 0.8 0.2VDD -- -- 0.4 0.4 1/-1 1/-250 15/-15 -- -- -- -- 2 -- -- 10 100
Unit
L Level Input Voltage 2, 4, 5, 6, 7
V
A
mA
Output Leakage Current 1, 2, 4
A pF A
mA
1. 2. 3. 4. 5. 6. 7. *1 *2
Applied to P0 Applied to P1 to P7 (except P3_0/ALE, P3_1/PSEN, P7_0/WR, P7_1/RD) Applied to AIN Applied to P3_0/ALE, P3_1/PSEN, P7_0/WR, P7_1/RD Applied to RES Applied to EA Applied to OSC0 Ports for input pins are VDD or GND, otherwise no load. Indicates the current consumption when A/D converter is not operating. When A/D convertion is operating current is consumed max. 2 mA more than that when it is not operating.
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Semiconductor AC Characteristics (Preliminary) * External program memory control
MSM66562/66P563
(VDD=5 V10%, Ta=-40 to +85C) Parameter Clock (OSC) pulse width ALE pulse width PSEN pulse width PSEN pulse delay time Low-order address set-up time Low-order address hold time High-order address set-up time High-order address hold time Instruction set-up time Instruction hold time Symbol toW tAW tPW tPAD tALS tALH tAHS tAPH tIS tIH CL=50 pF Condition -- Min. 25 2toW-10 2toW-10 toW-10 2toW-10 toW-10 3toW-10 Max. -- -- -- toW+10 2toW+10 toW+10 3toW+10 toW+10 -- toW-10 nsec Unit
CLK toW ALE tAW PSEN tPAD AD 0-7 PC 0-7 tALS A 8-14 tAHS tALH PC 8-14 tAPH tPW INST 0-7 tIS tIH toW
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Semiconductor
MSM66562/66P563
A/D CONVERTER CHARACTERISTICS (Preliminary)
(Ta=-40 to +85C, VDD=5 V10%, GND=0 V, fOSC=20 MHz) Parameter Resolution Linearity Error Differential Linearity Error Zero Scale Error Full Scale Error Crosstalk Conversion Time Symbol n EL ED EZS EFS ECT tCONV Condition Refer to the recommended circuit. Analog input source impedance RI 5 kW tCONV=19.2 msec Refer to the measuring circuit. by ADTM set data Min. -- -- -- -- -- 6.4 Typ. -- -- -- -- -- -- - 19.2 s/CH LSB Max. 8 Unit Bit
VDD
+
+5V
MSM66562
- +
RI
AI 0-5
0.1 mF
47 mF
Analog input
GND
0.1 mF
0V
RI (Analog input source impedance) 5 kW
Recommended Circuit
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Semiconductor
MSM66562/66P563
- + Analog input
~
5 kW AI0 AI1 0.1mF
Crosstalk is defined as the difference between the A/D conversion result when applying the identical analog input to AI0 to AI5 and the A/D conversion result in the circuit in the left figure.
AI5
VDD or GND
Crosstalk Measuring Circuit
Definitions of Terms
Resolution The minimum distinguishable analog input value. For 8 bits, 28=256, i.e. (VDD-GND) / 256. Linearity error The variance between the ideal conversion characteristics as a 8-bit A/D converter and the actual conversion characteristics. (Quantized error is therefore not included.) In the ideal conversion, a voltage between VDD and GND is divided into 256 equal steps. Differential linearity error The smoothness of the conversion. The width of analog input voltage corresponding to the change by one bit of digital output is 1 LSB=(VDD-GND) / 256 ideally. The variance between this ideal bit size and bit size at arbitrary point in the conversion range. Zero scale error The variance between the ideal conversion characteristics at the switching point of digital output "00H to 01H" and actual conversion characteristics. Full scale error The variance between the ideal conversion characteristics at the switching point of digital output "0FEH to 0FFH" and actual conversion characteristics.
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Semiconductor
MSM66562/66P563
PACKAGE DIMENSIONS
(Unit : mm)
SDIP42-P-600-1.78
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 4.52 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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Semiconductor
MSM66562/66P563
(Unit : mm)
QFP64-P-1414-0.80-BK
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.87 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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